Department of Electrical and Computer Engineering, Micro and Nanotechnology Laboratory, University of Illinois, Urbana, Illinois 61801, USA.
Nano Lett. 2013 Jun 12;13(6):2548-52. doi: 10.1021/nl400620f. Epub 2013 May 14.
High-quality growth of planar GaAs nanowires (NWs) with widths as small as 35 nm is realized by comprehensively mapping the parameter space of group III flow, V/III ratio, and temperature as the size of the NWs scales down. Using a growth mode modulation scheme for the NW and thin film barrier layers, monolithically integrated AlGaAs barrier-all-around planar GaAs NW high electron mobility transistors (NW-HEMTs) are achieved. The peak extrinsic transconductance, drive current, and effective electron velocity are 550 μS/μm, 435 μA/μm, and ~2.9 × 10(7) cm/s, respectively, at 2 V supply voltage with a gate length of 120 nm. The excellent DC performance demonstrated here shows the potential of this bottom-up planar NW technology for low-power high-speed very-large-scale-integration (VLSI) circuits.
通过全面绘制 III 族流量、V/III 比和温度参数空间的图谱,实现了宽度小至 35nm 的平面 GaAs 纳米线 (NW) 的高质量生长,随着 NW 尺寸的缩小。采用 NW 和薄膜势垒层的生长模式调制方案,实现了单片集成的 AlGaAs 势垒环绕平面 GaAs NW 高电子迁移率晶体管 (NW-HEMT)。在栅长为 120nm、2V 电源电压下,峰值外导纳、驱动电流和有效电子速度分别为 550μS/μm、435μA/μm 和~2.9×10(7)cm/s。这里展示的出色的直流性能表明,这种自下而上的平面 NW 技术具有用于低功耗高速超大规模集成电路 (VLSI) 电路的潜力。