Logic Computing Field-Effect Transistors Based on a Monolayer WSe Homojunction for the Semi-adder and Decoder.

Two-dimensional reconfigurable field-effect transistors (FETs) are promising candidates for next-generation computing hardware. However, exploring the cascade design of FETs for logic computing remains challenging. Here, by using density functional theory combined with the nonequilibrium Green's function method, we design a 5 nm split-gate FET based on a monolayer WSe homojunction, which can implement dynamic polarity control in different gate configurations. The series array of two FETs shows a functional family of logic gates (NOR, AND, XOR, , and ), and the semi-adder designed by the logic functions AND and XOR reduces the number of transistors by 66.7%. The parallel array of two FETs demonstrates reconfigurable logic gates with NAND/OR// quadruple functions, which can realize the decoding function of 00-11 in the decoder. The cascade design of the electrically tunable FETs helps to tackle the logic device downscaling and integration dilemmas.