Lee Minjong, Jung Yong Chan, Kim Jin-Hyun, Narayan Dushyant M, Kang Sehun, Park Woo Young, Im Kivin, Kim Jiyoung
Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, 75080, USA.
Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX, 75080, USA.
Nano Converg. 2025 Mar 6;12(1):15. doi: 10.1186/s40580-025-00477-2.
This study investigates the impact of dopants on HfZrO-based capacitors for high-performance, hysteresis-free dielectric applications. Control of the crystalline structure of HfZrO films is crucial for achieving superior dielectric properties. The tetragonal (t) phase of HfZrO exhibits anti-ferroelectric (AFE) characteristics and shows promise due to its high dielectric constant (κ). However, hysteresis behavior in polarization-voltage sweeps due to AFE behavior presents a significant challenge, primarily due to the high energy loss when implemented in dynamic random-access-memory (DRAM) applications. To achieve hysteresis-free operation, this study focuses on suppressing AFE switching within the DRAM voltage range through Si or La doping in HfZrO films. Introducing small amounts of Si or La (< 1%) into HfZrO capacitors effectively diminishes AFE switching by influencing which structural phases are favored: Si doping tends to favor the amorphous phase, while La doping promotes the formation of the t-phase. La doping shows particular promise in enhancing pseudo-linear dielectric performance. ~ 0.9% La-doped HfZrO capacitors exhibit a markedly improved equivalent oxide thickness (EOT) of ~ 4.8 Å and a reduced leakage current density (J) of ~ 10 A/cm at 1 V, achieved at back-end-of-line (BEOL) compatible temperatures (< 400 °C). These results demonstrate a promising strategy for advancing energy-efficient high-κ dielectric materials in next-generation memory devices, offering a balanced combination of high capacitance, low leakage current, and BEOL compatibility.
本研究调查了掺杂剂对用于高性能、无滞后介电应用的基于HfZrO的电容器的影响。控制HfZrO薄膜的晶体结构对于实现优异的介电性能至关重要。HfZrO的四方(t)相表现出反铁电(AFE)特性,并且由于其高介电常数(κ)而显示出应用前景。然而,由于AFE行为导致的极化-电压扫描中的滞后行为带来了重大挑战,这主要是因为在动态随机存取存储器(DRAM)应用中实施时能量损失很高。为了实现无滞后操作,本研究专注于通过在HfZrO薄膜中掺杂Si或La来抑制DRAM电压范围内的AFE开关。在HfZrO电容器中引入少量的Si或La(<1%)通过影响有利于哪些结构相而有效地减少了AFE开关:Si掺杂倾向于有利于非晶相,而La掺杂促进t相的形成。La掺杂在增强伪线性介电性能方面显示出特别的前景。~0.9% La掺杂的HfZrO电容器在后端线路(BEOL)兼容温度(<400°C)下实现了显著改善的等效氧化层厚度(EOT),约为4.8 Å,以及在1 V时降低的漏电流密度(J),约为10 A/cm。这些结果证明了一种在下一代存储器件中推进节能高κ介电材料的有前景的策略,提供了高电容、低漏电流和BEOL兼容性的平衡组合。