Hikawa Hiroomi
Department of Computer Science and Intelligent Systems, Oita University, Oita 870-1192, Japan.
Neural Netw. 2005 Jun-Jul;18(5-6):514-22. doi: 10.1016/j.neunet.2005.06.012.
The self-organizing map (SOM) has found applicability in a wide range of application areas. Recently new SOM hardware with phase modulated pulse signal and digital phase-locked loops (DPLLs) has been proposed (Hikawa, 2005). The system uses the DPLL as a computing element since the operation of the DPLL is very similar to that of SOM's computation. The system also uses square waveform phase to hold the value of the each input vector element. This paper discuss the hardware implementation of the DPLL SOM architecture. For effective hardware implementation, some components are redesigned to reduce the circuit size. The proposed SOM architecture is described in VHDL and implemented on field programmable gate array (FPGA). Its feasibility is verified by experiments. Results show that the proposed SOM implemented on the FPGA has a good quantization capability, and its circuit size very small.
自组织映射（SOM）已在广泛的应用领域中得到应用。最近，有人提出了一种采用相位调制脉冲信号和数字锁相环（DPLL）的新型SOM硬件（Hikawa，2005年）。该系统将DPLL用作计算元件，因为DPLL的操作与SOM的计算操作非常相似。该系统还使用方波相位来保持每个输入向量元素的值。本文讨论了DPLL SOM架构的硬件实现。为了实现有效的硬件实现，对一些组件进行了重新设计以减小电路尺寸。所提出的SOM架构用VHDL进行了描述，并在现场可编程门阵列（FPGA）上实现。通过实验验证了其可行性。结果表明，在FPGA上实现的所提出的SOM具有良好的量化能力，并且其电路尺寸非常小。
