FHAST:基于现场可编程门阵列(FPGA)的硬件中蝴蝶结(Bowtie)加速
FHAST: FPGA-Based Acceleration of Bowtie in Hardware.
作者信息
Fernandez Edward B, Villarreal Jason, Lonardi Stefano, Najjar Walid A
出版信息
IEEE/ACM Trans Comput Biol Bioinform. 2015 Sep-Oct;12(5):973-81. doi: 10.1109/TCBB.2015.2405333.
While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., Bowtie, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for Bowtie that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHAST running on the Convey HC-1 achieved up to 70x speedup compared to Bowtie (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to Bowtie running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for Bowtie, so it can be incorporated in any analysis pipeline that uses Bowtie (e.g., TopHat).
尽管现代仪器的测序能力持续呈指数级增长,但将短测序读段映射到参考基因组的计算问题仍然是分析流程中的一个瓶颈。对于通用计算机架构,有多种映射工具(如Bowtie、BWA)可供使用。根据输入读段的数量、参考基因组的大小以及允许的错配或插入/缺失数量,这些工具可能需要数小时甚至数天才能给出映射结果,这使得映射问题成为硬件加速的理想候选对象。在本文中,我们展示了FHAST(FPGA硬件加速序列匹配工具),它是Bowtie的直接替代工具,采用基于现场可编程门阵列(FPGA)的硬件设计。我们的架构通过同时执行多个并发访问内存的硬件线程来掩盖内存延迟。FHAST由多个并行引擎组成,以利用FPGA上的可用并行性。我们已经在Convey HC-1上实现并测试了FHAST,随后将其移植到Convey HC-2ex上,利用了这些系统的大内存带宽以及硬件和软件之间的共享内存映像。在Convey HC-1上运行的FHAST初步版本与Bowtie(单线程)相比,加速比高达70倍。在Convey HC-2ex FPGA上运行的改进版FHAST与在八核传统架构上运行八个线程的Bowtie相比,速度提升了12倍,同时保持了几乎相同的映射精度。FHAST是Bowtie的直接替代工具,因此可以纳入任何使用Bowtie的分析流程(如TopHat)。