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基于椭圆谐振器的纳米级等离子体组合逻辑电路。

Nanoscale plasmonic combinational logic circuits based on an elliptical resonator.

作者信息

Alali Mohammed J, Raheema Mithaq Nama, Alwahib Ali A

出版信息

Appl Opt. 2023 Jul 1;62(19):5107-5114. doi: 10.1364/AO.495518.

Abstract

The half-adder (HA) and half-subtractor (HS) plasmonic combinational logic circuits are explained using a finite element method with a COMSOL software package. The combinational circuits are created using insulator-metal-insulator technology with nanoscale plasmonic structures. In order to achieve an excellent transmission value, the phase angle of optical waves and the position of the control and input ports are the more crucial elements. In this design, the nanoscale combinational circuits are realized at a 35% transmission threshold to distinguish between the logic "0" and logic "1" stand on the interference between the input and control ports with 540 ×250 dimensions and an 850 nm resonant wavelength. The modulation depth, contrast ratio, and insertion loss have 97.38%, and 11.84 and 3.3 dB for the HA, and they have 92.38%, and 7.12 and -1.41 for the HS, respectively.

摘要

采用COMSOL软件包中的有限元方法对半加器(HA)和半减器(HS)等离子体组合逻辑电路进行了说明。这些组合电路是使用具有纳米级等离子体结构的绝缘体-金属-绝缘体技术创建的。为了获得优异的传输值,光波的相位角以及控制端口和输入端口的位置是更为关键的因素。在本设计中,纳米级组合电路在35%的传输阈值下实现,以基于540×250尺寸和850 nm共振波长的输入端口与控制端口之间的干涉来区分逻辑“0”和逻辑“1”。对于HA,调制深度、对比度和插入损耗分别为97.38%、11.84和3.3 dB;对于HS,它们分别为92.38%、7.12和-1.41。

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