Verma Gaurav, Soni Sandeep, Kaushik Brajesh Kumar
Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, Uttarakhand-247667, India.
Cadence Design Systems, NSEZ, Noida, 201307, India.
Nanotechnology. 2023 Nov 15;35(5). doi: 10.1088/1361-6528/ad0056.
Artificial intelligence and deep learning today are utilized for several applications namely image processing, smart surveillance, edge computing, and so on. The hardware implementation of such applications has been a matter of concern due to huge area and energy requirements. The concept of computing in-memory and the use of non-volatile memory (NVM) devices have paved a path for resource-efficient hardware implementation. We propose a dual-level spin-orbit torque magnetic random-access memory (SOT-DLC MRAM) based crossbar array design for image edge detection. The presented in-memory edge detection algorithm framework provides spin-based crossbar designs that can intrinsically perform image edge detection in an energy-efficient manner. The simulation results are scaled down in energy consumption for data transfer by a factor of 8x for grayscale images with a comparatively smaller crossbar than an equivalent CMOS design. DLC SOT-MRAM outperforms CMOS-based hardware implementation in several key aspects, offering 1.53x greater area efficiency, 14.24x lower leakage power dissipation, and 3.63x improved energy efficiency. Additionally, when compared to conventional spin transfer torque (STT-MRAM and SOT-MRAM, SOT-DLC MRAM achieves higher energy efficiency with a 1.07x and 1.03x advantage, respectively. Further, we extended the image edge extraction framework to spiking domain where ant colony optimization (ACO) algorithm is implemented. The mathematical analysis is presented for mapping of conductance matrix of the crossbar during edge detection with an improved area and energy efficiency at hardware implementation. The pixel accuracy of edge-detected image from ACO is 4.9% and 3.72% higher than conventional Sobel and Canny based edge-detection.
如今，人工智能和深度学习被应用于多个领域，如图像处理、智能监控、边缘计算等。由于此类应用对面积和能量的巨大需求，其硬件实现一直备受关注。内存计算的概念以及非易失性存储器（NVM）设备的使用为资源高效的硬件实现铺平了道路。我们提出了一种基于双层自旋轨道扭矩磁性随机存取存储器（SOT-DLC MRAM）的交叉阵列设计用于图像边缘检测。所提出的内存边缘检测算法框架提供了基于自旋的交叉阵列设计，能够以节能的方式内在地执行图像边缘检测。对于灰度图像，与等效的CMOS设计相比，所呈现的交叉阵列在数据传输能耗方面降低了8倍，且交叉阵列尺寸相对较小。DLC SOT-MRAM在几个关键方面优于基于CMOS的硬件实现，面积效率提高了1.53倍，泄漏功耗降低了14.24倍，能量效率提高了3.63倍。此外，与传统的自旋转移扭矩（STT-MRAM和SOT-MRAM）相比，SOT-DLC MRAM分别具有1.07倍和1.03倍的优势，实现了更高的能量效率。此外，我们将图像边缘提取框架扩展到了实现蚁群优化（ACO）算法的脉冲域。给出了在硬件实现中边缘检测期间交叉阵列电导矩阵映射的数学分析，具有改进的面积和能量效率。来自ACO的边缘检测图像的像素精度比基于传统Sobel和Canny的边缘检测分别高4.9%和3.72%。
