Yan Xiao-lang, Yu Long-li, Wang Jie-bing
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China.
J Zhejiang Univ Sci. 2004 Sep;5(9):1102-5. doi: 10.1631/jzus.2004.1102.
This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.
本文描述了一种内部开发的语言工具VPerl，它用于开发一款250MHz 32位高性能低功耗嵌入式CPU内核。作者表明，使用该工具可以将Verilog代码压缩5倍以上，提高前端设计效率，显著降低错误率。该工具可用于提高知识产权模型的可重用性，并便于针对不同平台进行移植设计。
