Oshida Nobuhiko, Ihara Sigeo
Department of Advanced Interdisciplinary Studies, and Research Center for Advanced Science and Technology, The University of Tokyo, Tokyo 153-8904, Japan.
Phys Rev E Stat Nonlin Soft Matter Phys. 2006 Aug;74(2 Pt 2):026115. doi: 10.1103/PhysRevE.74.026115. Epub 2006 Aug 18.
Recent progress in integrated circuit technologies requires precise evaluation between dynamic characteristics and topological architecture design. In this paper, we have investigated the performance evaluation of network-on-chip (NoC) architectures constructed with diverse scale-free network topologies by dynamic packet traffic simulation and theoretical network analysis. Topological differences of scale-free networks are evaluated by the degree-degree correlations that indicate topological tendency between the degree of a node and that of the nearest neighbors. Our simulation results quantitatively show that the NoC architecture constructed with the topology where hubs mostly connect to lower-degree nodes is found to achieve short latency and low packet loss ratio since it can disperse traffic load and avoid the extreme concentration of load on hubs.
集成电路技术的最新进展要求在动态特性和拓扑架构设计之间进行精确评估。在本文中，我们通过动态数据包流量模拟和理论网络分析，研究了由不同无标度网络拓扑构建的片上网络（NoC）架构的性能评估。无标度网络的拓扑差异通过度-度相关性来评估，该相关性指示节点的度与其最近邻节点的度之间的拓扑趋势。我们的模拟结果定量地表明，发现用集线器大多连接到低度数节点的拓扑构建的NoC架构能够实现短延迟和低丢包率，因为它可以分散流量负载并避免负载在集线器上的极端集中。
