Díaz Javier, Ros Eduardo, Carrillo Richard, Prieto Alberto
IEEE Trans Image Process. 2007 Jan;16(1):280-5. doi: 10.1109/tip.2006.884931.
We present the hardware implementation of a simple, fast technique for depth estimation based on phase measurement. This technique avoids the problem of phase warping and is much less susceptible to camera noise and distortion than standard block-matching stereo systems. The architecture exploits the parallel computing resources of FPGA devices to achieve a computation speed of 65 megapixels per second. For this purpose, we have designed a fine-grain pipeline structure that can be arranged with a customized frame-grabber module to process 52 frames per second at a resolution of 1280 x 960 pixels. We have measured the system's degradation due to bit quantization errors and compared its performance with other previous approaches. We have also used different Gabor-scale circuits, which can be selected by the user according to the application addressed and typical image structure in the target scenario.
我们展示了一种基于相位测量的简单、快速深度估计技术的硬件实现。该技术避免了相位扭曲问题，并且与标准的块匹配立体系统相比，对相机噪声和失真的敏感度要低得多。该架构利用FPGA设备的并行计算资源，实现了每秒65兆像素的计算速度。为此，我们设计了一种细粒度流水线结构，该结构可与定制的帧捕捉模块配合使用，以1280×960像素的分辨率每秒处理52帧。我们测量了由于位量化误差导致的系统性能下降，并将其性能与其他先前的方法进行了比较。我们还使用了不同的伽柏尺度电路，用户可以根据所处理的应用和目标场景中的典型图像结构来选择。
