Li Limin, Wyrwicz Alice M
Center for Basic MR Research, NorthShore University HealthSystem Research Institute, Evanston, IL, USA.
Center for Basic MR Research, NorthShore University HealthSystem Research Institute, Evanston, IL, USA; Department of Biomedical Engineering, Northwestern University, Evanston, IL, USA.
J Magn Reson. 2015 Jun;255:51-8. doi: 10.1016/j.jmr.2015.03.007. Epub 2015 Mar 23.
We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128×128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments.
我们描述了一种用于实时图像处理的单芯片现场可编程门阵列（FPGA）上的图像处理模块的设计与实现。我们还证明，通过图形编码，设计工作可以大大简化。该处理模块基于二维快速傅里叶变换（2D FFT）核。我们的设计在两个方面与先前报道的设计不同。无需片外硬件资源，这增加了内核的可移植性。使用我们新设计的地址生成单元完全避免了二维快速傅里叶变换执行通常所需的直接矩阵转置，这节省了大量片上块随机存取存储器（block RAM）和时钟周期。通过从体模和动物数据重建多层磁共振（MR）图像对图像处理模块进行了测试。对静态数据的测试表明，该处理模块能够以400帧/秒的速度重建128×128的图像。对模拟实时流数据的测试表明，该模块在MRI实验所需的定时条件下能正常工作。
