Qiushi Academy for Advanced Studies, Zhejiang University, Hangzhou 310027, PR China.
J Neurosci Methods. 2010 Jan 15;185(2):299-306. doi: 10.1016/j.jneumeth.2009.10.001. Epub 2009 Oct 29.
A practical brain-machine interface (BMI) requires real-time decoding algorithms to be realised in a portable device rather than a personal computer. In this article, a field-programmable gate array (FPGA) implementation of a probabilistic neural network (PNN) is proposed and developed to decode motor cortical ensemble recordings in rats performing a lever-pressing task for water rewards. A chronic 16-channel microelectrode array was implanted into the primary motor cortex of the rat to record neural activity, and the pressure signal of the lever were recorded simultaneously. To decode the pressure value from neural activity, both Matlab-based and FPGA-based mapping algorithms using a PNN were implemented and evaluated. In the FPGA architecture, training data of the network were stored in random access memory (RAM) blocks and multiply-add operations were realised by on-chip DSP48E slices. In the approximation of the activation function, a Taylor series and a look-up table (LUT) are used to achieve an accurate approximation. The results of FPGA implementation are as accurate as the realisation of Matlab, but the running speed is 37.9 times faster. This novel and feasible method indicates that the performance of current FPGAs is competent for portable BMI applications.
实用的脑机接口 (BMI) 需要在便携式设备而不是个人计算机中实现实时解码算法。在本文中，提出并开发了一种现场可编程门阵列 (FPGA) 实现的概率神经网络 (PNN)，用于解码大鼠执行 lever-pressing 任务以获取水奖励时的运动皮质组合记录。将一个慢性 16 通道微电极阵列植入大鼠的初级运动皮层以记录神经活动，并同时记录 lever 的压力信号。为了解码神经活动中的压力值，使用 PNN 实现并评估了基于 Matlab 和基于 FPGA 的映射算法。在 FPGA 架构中，网络的训练数据存储在随机存取存储器 (RAM) 块中，并且通过片上 DSP48E 切片实现乘法-累加操作。在激活函数的逼近中，使用泰勒级数和查找表 (LUT) 来实现精确逼近。FPGA 实现的结果与 Matlab 的实现一样准确，但运行速度快 37.9 倍。这种新颖且可行的方法表明，当前 FPGA 的性能能够胜任便携式 BMI 应用。
