McCormick F B, Cloonan T J, Lentine A L, Sasian J M, Morrison R L, Beckman M G, Walker S L, Wojcik M J, Hinterlong S J, Crisci R J, Novotny R A, Hinton H S
Appl Opt. 1994 Mar 10;33(8):1601-18. doi: 10.1364/AO.33.001601.
The design, construction, and operational testing of a five-stage, fully interconnected 32 × 16 switching fabric by the use of smart-pixel (2, 1, 1) switching nodes are described. The arrays of switching nodes use monolithically integrated GaAs field-effect transistors, multiple-quantum-well p-i-n detectors, and self-electro-optic-device modulators. Each switching node incorporates 25 field-effect transistors and 17 p-i-n diodes to realize two differential optical receivers, the 2 × 1 node switching logic, a single-bit node control memory, and one differential optical transmitter. The five stages of node arrays are interconnected to form a two-dimensional banyan network by the use of Fourier-plane computer-generated holograms. System input and output are made by two-dimensional fiber-bundle matrices, and the system optical hardware design incorporates frequency-stabilized lasers, pupil-division beam combination, and a hybrid micro-macro lens for fiber-bundle imaging. Optomechanical packaging of the system ut lizes modular kinematic component positioning and active thermal control to enable simple rapid assembly. Two preliminary operational experiments are completed. In the first experiment, five stages are operated at 50 Mbits/s with 15 active inputs and outputs. The second experiment attempts to operate two stages of second-generation node arrays at 155 Mbits/s, with eight of the 15 active nodes functioning correctly along the straight switch-routing paths.
本文描述了一种使用智能像素(2,1,1)交换节点设计、构建并进行操作测试的五级、全互连32×16交换结构。交换节点阵列采用单片集成的砷化镓场效应晶体管、多量子阱p-i-n探测器和自电光器件调制器。每个交换节点包含25个场效应晶体管和17个p-i-n二极管，以实现两个差分光接收器、2×1节点交换逻辑、一个单比特节点控制存储器和一个差分光发射器。节点阵列的五个阶段通过使用傅里叶平面计算机生成全息图互连，形成二维榕树网络。系统输入和输出由二维光纤束矩阵实现，并且系统光学硬件设计包括频率稳定激光器、光瞳分割光束组合以及用于光纤束成像的混合微宏透镜。系统的光机械封装采用模块化运动部件定位和主动热控制，以实现简单快速的组装。完成了两个初步操作实验。在第一个实验中，五个阶段以50 Mbit/s的速率运行，有15个有源输入和输出。第二个实验尝试以155 Mbit/s的速率运行两代节点阵列中的两个阶段，15个有源节点中有8个在直线路径上正确运行。
