Ryu Ju Tae, You Joo Hyung, Yoo Keon-Ho, Kim Tae Whan
Department of Electronic and Computer Engineering, Hanyang University, Seoul 133-791, Korea.
J Nanosci Nanotechnol. 2011 Aug;11(8):7512-5. doi: 10.1166/jnn.2011.4844.
NAND silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with double gates fabricated on silicon-on-insulator (SOI) substrates were proposed. The current-voltage characteristics related to the programming operation of the designed nanoscale NAND SONOS flash memory devices on a SOI substrate and on the conventional bulk-Si substrate were simulated and compared in order to investigate device characteristics of the scaled-down memory devices. The simulation results showed that the short channel effect and the subthreshod leakage current for the memory device with a large spacer length were lower than that of the memory device with a small spacer length due to increase of the effective channel length. The device performance of the memory device utilizing the SOI substrate exhibited a smaller subthreshold swing and a larger drain current level in comparison with those on the bulk-Si substrate. These improved electrical characteristices for the SOI devices could be explained by comparing the electric field distribution in a channel region for both devices.
提出了在绝缘体上硅（SOI）衬底上制造的具有双栅极的与非型氧化硅-氮化物-氧化物-硅（SONOS）闪存器件。为了研究按比例缩小的存储器件的器件特性，对在SOI衬底和传统体硅衬底上设计的纳米级与非型SONOS闪存器件的编程操作相关的电流-电压特性进行了模拟和比较。模拟结果表明，由于有效沟道长度的增加，具有大间隔长度的存储器件的短沟道效应和亚阈值泄漏电流低于具有小间隔长度的存储器件。与体硅衬底上的存储器件相比，利用SOI衬底的存储器件的器件性能表现出更小的亚阈值摆幅和更大的漏极电流水平。通过比较两种器件沟道区域中的电场分布，可以解释SOI器件这些改善的电学特性。
