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使用基于 SRAM 的 FPGA 实现节能型高性能无线传感器网络。

Using SRAM based FPGAs for power-aware high performance wireless sensor networks.

机构信息

Centro de Electronica Industrial, Universidad Politecnica de Madrid, Madrid 28006, Spain.

出版信息

Sensors (Basel). 2012;12(3):2667-92. doi: 10.3390/s120302667. Epub 2012 Feb 28.

DOI:10.3390/s120302667
PMID:22736971
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC3376580/
Abstract

While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today's applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements.

摘要

多年来,传统的无线传感器节点一直基于具有足够但有限计算能力的超低功耗微控制器,而当今应用的复杂性和任务数量却在不断增加。在所有情况下增加节点的占空比都是不可行的,因此在许多情况下需要更多的计算能力。这种额外的计算能力可以通过更强大的微控制器来实现,尽管功耗更高,或者通常来说,任何能够加速任务执行的解决方案。此时,基于硬件的解决方案,特别是 FPGA 解决方案,可能成为一个候选技术,因为虽然与低功耗设备相比,其功耗更高,但执行时间缩短,因此总体上可以减少能源消耗。为了证明这一点,提出了一种创新的 WSN 节点架构。该架构基于一种高性能大容量的最先进 FPGA,它结合了硬件设备并行性提供的内在加速优势、部分重配置功能的使用以及精心的节能管理系统,以证明对于某些高端应用程序可以实现节能。最后,进行了全面的测试,以验证平台在性能和功耗方面的表现,证明与基于处理器的解决方案相比,它可以实现更高的能效,例如,当应用程序要求加密时。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/5ea53222268f/sensors-12-02667f18.jpg
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https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/5ea53222268f/sensors-12-02667f18.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/68121bca1034/sensors-12-02667f1.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/a1234bb996e1/sensors-12-02667f2.jpg
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https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/da56f3d714b7/sensors-12-02667f6.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/e51967a7cd9c/sensors-12-02667f7.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/b86302777380/sensors-12-02667f8.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/5a4da3defd46/sensors-12-02667f9.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/3d52f79c68f5/sensors-12-02667f10.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/917cd97fa8e5/sensors-12-02667f11.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/d7c5628ec9f7/sensors-12-02667f12.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/8577f356b1e6/sensors-12-02667f13.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/01e1dc154d6c/sensors-12-02667f14.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/c9d06c7dc449/sensors-12-02667f15.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/77a8b447494c/sensors-12-02667f16.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/8022ea0c640c/sensors-12-02667f17.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/13a3/3376580/5ea53222268f/sensors-12-02667f18.jpg

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