Sun Min-Chul, Kim Garam, Kim Sang Wan, Kim Hyun Woo, Kim Hyungjin, Lee Jong-Ho, Shin Hyungcheol, Park Byung-Gook
Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, Seoul 151-744, South Korea.
J Nanosci Nanotechnol. 2012 Jul;12(7):5313-7. doi: 10.1166/jnn.2012.6226.
In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.
为了在不使用绝缘体上硅（SOI）衬底的情况下将传统的低功耗硅互补金属氧化物半导体（CMOS）技术扩展到20纳米节点以上，我们提出了一种新颖的共集成方案，将水平和垂直沟道金属氧化物半导体场效应晶体管（MOSFET）集成在一起，并使用TCAD模拟验证了这一想法。从制造角度来看，值得注意的是，该方案通过在传统CMOS工艺流程中增加几个用于鳍片形成的步骤，为额外的垂直器件提供了良好的可扩展性。此外，使用TCAD器件模拟研究了共集成垂直器件的优势。通过这项研究证实，由于双栅极沟道处的电场耦合效应，当体尺寸小于20纳米时，垂直器件的关态电流控制得到改善，驱动电流更大。最后，通过混合模式电路模拟研究证实了从电路设计角度来看的优势，如更大的中点增益和β以及更低的功耗。
