Ni Fan, Long Xiang, Wan Han, Gao Xiaopeng
School of Computer Science and Engineering, Beihang University, Beijing, China.
PLoS One. 2013 Dec 26;8(12):e82975. doi: 10.1371/journal.pone.0082975. eCollection 2013.
Caches play an important role in embedded systems to bridge the performance gap between fast processor and slow memory. And prefetching mechanisms are proposed to further improve the cache performance. While in real-time systems, the application of caches complicates the Worst-Case Execution Time (WCET) analysis due to its unpredictable behavior. Modern embedded processors often equip locking mechanism to improve timing predictability of the instruction cache. However, locking the whole cache may degrade the cache performance and increase the WCET of the real-time application. In this paper, we proposed an instruction-prefetching combined partial cache locking mechanism, which combines an instruction prefetching mechanism (termed as BBIP) with partial cache locking to improve the WCET estimates of real-time applications. BBIP is an instruction prefetching mechanism we have already proposed to improve the worst-case cache performance and in turn the worst-case execution time. The estimations on typical real-time applications show that the partial cache locking mechanism shows remarkable WCET improvement over static analysis and full cache locking.
高速缓存（Caches）在嵌入式系统中起着重要作用，以弥合快速处理器和慢速内存之间的性能差距。并且提出了预取机制以进一步提高高速缓存性能。然而在实时系统中，由于高速缓存行为不可预测，其应用使最坏情况执行时间（WCET）分析变得复杂。现代嵌入式处理器通常配备锁定机制以提高指令高速缓存的时序可预测性。但是，锁定整个高速缓存可能会降低高速缓存性能并增加实时应用程序的WCET。在本文中，我们提出了一种指令预取与部分高速缓存锁定相结合的机制，该机制将指令预取机制（称为BBIP）与部分高速缓存锁定相结合，以改善实时应用程序的WCET估计。BBIP是我们已经提出的一种指令预取机制，用于改善最坏情况的高速缓存性能，进而改善最坏情况执行时间。对典型实时应用程序的估计表明，部分高速缓存锁定机制相对于静态分析和全高速缓存锁定在WCET方面有显著改进。
