A 16 GHz silicon-based monolithic balanced photodetector with on-chip capacitors for 25 Gbaud front-end receivers.

In this paper, a Germanium-on-Silicon balanced photodetector (BPD) with integrated biasing capacitors is demonstrated for highly compact monolithic 100 Gb/s coherent receivers or 25 Gbaud front-end receivers for differential or quadrature phase shift keying. The balanced photodetector has a bandwidth of approximately 16.2 GHz at a reverse bias of -4.5 V. The balanced photodetector exhibits a common mode rejection ratio (CMRR) of 30 dB. For balanced detection of return-to-zero (RZ) differential phase shift keying (DPSK) signal, the photodetector has a sensitivity of -6.95 dBm at the BER of 10(-12). For non-return-to-zero (NRZ) on off keying (OOK) signal, the measured BER is 1.0 × 10(-12) for a received power of -1.65 dBm at 25 Gb/s and 9.9 × 10(-5) for -0.34 dBm at 30 Gb/s. The total footprint area of the monolithic front-end receiver is less than 1 mm(2). The BPD is packaged onto a ceramic substrate with two DC and one RF connectors exhibits a bandwidth of 15.9 GHz.