Amit Iddo, Jeon Nari, Lauhon Lincoln J, Rosenwaks Yossi
Department of Physical Electronics-School of Electrical Engineering, Tel Aviv University , Ramat Aviv 69978, Tel Aviv, Israel.
Department of Materials Science and Engineering, Northwestern University , Evanston, Illinois 60208, United States.
ACS Appl Mater Interfaces. 2016 Jan 13;8(1):128-34. doi: 10.1021/acsami.5b07746. Epub 2015 Dec 22.
The modulation between different doping species required to produce a diode in VLS-grown nanowires (NWs) yields a complex doping profile, both axially and radially, and a gradual junction at the interface. We present a detailed analysis of the dopant distribution around the junction. By combining surface potential measurements, performed by KPFM, with finite element simulations, we show that the highly doped (5 × 10(19) cm(-3)) shell surrounding the NW can screen the junction's built in voltage at shell thickness as low as 3 nm. By comparing NWs with high and low doping contrast at the junction, we show that dopant compensation dramatically decreases the electrostatic width of the junction and results in relatively low leakage currents.
在通过气相-液-固（VLS）生长法制备纳米线（NWs）二极管时，不同掺杂物种之间的调制会在轴向和径向上产生复杂的掺杂分布，并在界面处形成渐变结。我们对结周围的掺杂剂分布进行了详细分析。通过结合开尔文探针力显微镜（KPFM）进行的表面电位测量和有限元模拟，我们表明，围绕纳米线的高掺杂（5×10¹⁹ cm⁻³）壳层在壳层厚度低至3 nm时就能屏蔽结的内建电压。通过比较结处具有高掺杂对比度和低掺杂对比度的纳米线，我们表明掺杂剂补偿会显著减小结的静电宽度，并导致相对较低的漏电流。
