Xiong Yuhua, Chen Xiaoqiang, Wei Feng, Du Jun, Zhao Hongbin, Tang Zhaoyun, Tang Bo, Wang Wenwu, Yan Jiang
Advanced Electronic Materials Institute, General Research Institute for Nonferrous Metals, Beijing, 100088, China.
Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, China.
Nanoscale Res Lett. 2016 Dec;11(1):533. doi: 10.1186/s11671-016-1754-5. Epub 2016 Nov 30.
Ultrathin Hf-Ti-O higher k gate dielectric films (2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm @ (V - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I /I ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO. With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I , I /I ratio in the magnitude of 10, and peak transconductance, as well as suitable threshold voltage (-0.3-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.
通过原子层沉积制备了超薄的Hf-Ti-O高k栅极介质膜(约2.55纳米)。研究了它们的电学性能及其在全耗尽超薄绝缘体上硅(ETSOI)PMOSFET中的应用。结果发现,当Ti/(Ti + Hf)的浓度约为9.4%时,可获得约0.69纳米的低等效栅氧化层厚度(EOT)以及在(V - 1)V时0.61 A/cm²的可接受的栅极漏电流密度。在-0.5至-2 V的栅极电压范围内,通过栅极介质的传导机制主要由F-N隧穿主导。在相同的物理厚度和工艺流程下,与HfO₂相比,使用Hf-Ti-O作为栅极介质时可获得更低的EOT和更高的Iₒ/Iₛ比。以Hf-Ti-O作为栅极介质,两个栅宽/栅长(W/L)分别为0.5μm/25nm和3μm/40nm的ETSOI PMOSFET表现出良好的性能,如高Iₒ、Iₒ/Iₛ比在10的量级、峰值跨导以及合适的阈值电压(-0.3~-0.2 V)。特别是,ETSOI PMOSFET表现出卓越的短沟道控制能力,漏极诱导势垒降低(DIBL)<82 mV/V,亚阈值摆幅<70 mV/十倍频程。