Paramasivam Pattunnarajam, Gowthaman Naveenbalaji, Srivastava Viranjay M
Department of Electronics and Communication Engineering, Prince Shri Venkateshwara Padmavathy Engineering College, Chennai, 600127, India.
Department of Electronic Engineering, Howard College, University of KwaZulu- Natal, Durban, 4041, South Africa.
Recent Pat Nanotechnol. 2024;18(3):335-349. doi: 10.2174/1872210517666230602095347.
The electrical behavior of a high-performance Indium Gallium Arsenide (In- GaAs) wafer-based n-type Double-Gate (DG) MOSFET with a gate length (L= L) of 2 nm was analyzed. The relationship of channel length, gate length, top and bottom gate oxide layer thickness, a gate oxide material, and the rectangular wafer with upgraded structural characteristics and the parameters, such as switch current ratio (I) and transconductance (G) was analyzed for hybrid RF applications.
This work was carried out at 300 K utilizing a Non-Equilibrium Green Function (NEGF) mechanism for the proposed DG MOSFET architecture with LaO(EOT=1 nm) as gate dielectric oxide and source-drain device length (L) of 45 nm. It resulted in a maximum drain current (ID) of 4.52 mA, where the drain-source voltage (V) varied between 0 V and 0.5 V at the fixed gate to source voltage (V) = 0.5 V. The ON current(I), leakage current (I), and (I) switching current ratios of 1.56 mA, 8.49×10 μA, and 18.3×10 μA were obtained when the gate to source voltage (V) varied between 0 and 0.5 V at fixed drain-source voltage (V)=0.5V.
The simulated result showed the values of maximum current density (J), one and twodimensional electron density (N and N), electron mobility (μ), transconductance (G), and Subthreshold Slope (SS) are 52.4 μA/m, 3.6×10 cm, 11.36×10 cm, 1417 cmVS, 3140 μS/μm, and 178 mV/dec, respectively. The Fermi-Dirac statistics were employed to limit the charge distribution of holes and electrons at a semiconductor-insulator interface. The flat-band voltage (V) of - 0.45 V for the fixed threshold voltage greatly impacted the breakdown voltage. The results were obtained by applying carriers to the channels with the (001) axis perpendicular to the gate oxide. The sub-band energy profile and electron density were well implemented and derived using the Non-Equilibrium Green's Function (NEGF) formalism. Further, a few advantages of the proposed heterostructure-based DG MOSFET structure over the other structures were observed.
This proposed patent design, with a reduction in the leakage current characteristics, is mainly suitable for advanced Silicon-based solid-state CMOS devices, Microelectronics, Nanotechnologies, and future-generation device applications.
分析了一种基于高性能砷化铟镓（In-GaAs）晶圆的n型双栅（DG）MOSFET的电学行为，该器件的栅长（L = L）为2纳米。针对混合射频应用，分析了沟道长度、栅长、顶部和底部栅氧化层厚度、栅氧化材料以及具有升级结构特性的矩形晶圆与开关电流比（I）和跨导（G）等参数之间的关系。
这项工作在300 K下利用非平衡格林函数（NEGF）机制对所提出的DG MOSFET架构进行，该架构采用LaO（等效氧化层厚度EOT = 1纳米）作为栅介质氧化物，源漏器件长度（L）为45纳米。在固定栅源电压（V）= 0.5 V时，漏源电压（V）在0 V至0.5 V之间变化，得到最大漏极电流（ID）为4.52 mA。当栅源电压（V）在固定漏源电压（V）= 0.5 V时在0至0.5 V之间变化时，获得的导通电流（I）、漏电流（I）和（I）开关电流比分别为1.56 mA、8.49×10 μA和18.3×10 μA。
模拟结果表明，最大电流密度（J）、一维和二维电子密度（N和N）、电子迁移率（μ）、跨导（G）和亚阈值斜率（SS）的值分别为52.4 μA/m、3.6×10 cm、11.36×10 cm、1417 cmVS、3140 μS/μm和178 mV/dec。采用费米-狄拉克统计来限制半导体-绝缘体界面处空穴和电子的电荷分布。固定阈值电压下-0.45 V的平带电压（V）对击穿电压有很大影响。通过将载流子施加到（001）轴垂直于栅氧化层的沟道中获得结果。利用非平衡格林函数（NEGF）形式很好地实现并推导了子带能量分布和电子密度。此外，观察到所提出的基于异质结构的DG MOSFET结构相对于其他结构的一些优点。
该专利设计具有降低漏电流特性的优点，主要适用于先进的硅基固态CMOS器件、微电子、纳米技术以及下一代器件应用。
