Shao Shuai, Liu Dapeng, Niu Yuling, O'Donnell Kathy, Sengupta Dipak, Park Seungbae
Department of Mechanical Engineering, State University of New York at Binghamton, P.O. Box 6000, Binghamton, NY 13902, USA.
Analog Devices, Inc., Wilmington, MA 01887, USA.
Sensors (Basel). 2017 Feb 9;17(2):322. doi: 10.3390/s17020322.
Reliability risks for two different types of through-silicon-vias (TSVs) are discussed in this paper. The first is a partially-filled copper TSV, if which the copper layer covers the side walls and bottom. A polymer is used to fill the rest of the cavity. Stresses in risk sites are studied and ranked for this TSV structure by FEA modeling. Parametric studies for material properties (modulus and thermal expansion) of TSV polymer are performed. The second type is a high aspect ratio TSV filled by polycrystalline silicon (poly Si). Potential risks of the voids in the poly Si due to filling defects are studied. Fracture mechanics methods are utilized to evaluate the risk for two different assembly conditions: package assembled to printed circuit board (PCB) and package assembled to flexible substrate. The effect of board/substrate/die thickness and the size and location of the void are discussed.
本文讨论了两种不同类型的硅通孔(TSV)的可靠性风险。第一种是部分填充铜的TSV,其铜层覆盖侧壁和底部。用聚合物填充其余的腔体。通过有限元分析(FEA)建模研究了该TSV结构风险部位的应力并进行了排序。对TSV聚合物的材料特性(模量和热膨胀)进行了参数研究。第二种类型是由多晶硅(poly Si)填充的高深径比TSV。研究了由于填充缺陷导致的多晶硅中孔隙的潜在风险。利用断裂力学方法评估了两种不同组装条件下的风险:封装组装到印刷电路板(PCB)和封装组装到柔性基板。讨论了板/基板/芯片厚度以及孔隙的尺寸和位置的影响。