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基于插值CIC滤波器的超声相控阵高时延精度实现

Implementation of High Time Delay Accuracy of Ultrasonic Phased Array Based on Interpolation CIC Filter.

作者信息

Liu Peilu, Li Xinghua, Li Haopeng, Su Zhikun, Zhang Hongxu

机构信息

State Key Laboratory of Precision Measuring Technology and Instruments, Tianjin University, Tianjin 300072, China.

出版信息

Sensors (Basel). 2017 Oct 12;17(10):2322. doi: 10.3390/s17102322.

Abstract

In order to improve the accuracy of ultrasonic phased array focusing time delay, analyzing the original interpolation Cascade-Integrator-Comb (CIC) filter, an 8× interpolation CIC filter parallel algorithm was proposed, so that interpolation and multichannel decomposition can simultaneously process. Moreover, we summarized the general formula of arbitrary multiple interpolation CIC filter parallel algorithm and established an ultrasonic phased array focusing time delay system based on 8× interpolation CIC filter parallel algorithm. Improving the algorithmic structure, 12.5% of addition and 29.2% of multiplication was reduced, meanwhile the speed of computation is still very fast. Considering the existing problems of the CIC filter, we compensated the CIC filter; the compensated CIC filter's pass band is flatter, the transition band becomes steep, and the stop band attenuation increases. Finally, we verified the feasibility of this algorithm on Field Programming Gate Array (FPGA). In the case of system clock is 125 MHz, after 8× interpolation filtering and decomposition, time delay accuracy of the defect echo becomes 1 ns. Simulation and experimental results both show that the algorithm we proposed has strong feasibility. Because of the fast calculation, small computational amount and high resolution, this algorithm is especially suitable for applications with high time delay accuracy and fast detection.

摘要

为提高超声相控阵聚焦延时的精度,对原有的插值级联积分梳状(CIC)滤波器进行分析,提出一种8倍插值CIC滤波器并行算法,使插值与多通道分解能同时进行。此外,总结了任意倍数插值CIC滤波器并行算法的通用公式,并基于8倍插值CIC滤波器并行算法建立了超声相控阵聚焦延时系统。通过改进算法结构,加法运算减少了12.5%,乘法运算减少了29.2%,同时计算速度仍然很快。针对CIC滤波器存在的问题,对其进行了补偿;补偿后的CIC滤波器通带更平坦,过渡带变陡,阻带衰减增加。最后,在现场可编程门阵列(FPGA)上验证了该算法的可行性。在系统时钟为125MHz的情况下,经过8倍插值滤波和分解后,缺陷回波的延时精度达到1ns。仿真和实验结果均表明所提算法具有很强的可行性。由于计算速度快、计算量小且分辨率高,该算法特别适用于对延时精度要求高且检测速度快的应用场合。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/3246/5676649/30422b9c13db/sensors-17-02322-g017.jpg

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