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光刻制造的金纳米线波导用于等离子体激元器件和逻辑门。

Lithographically fabricated gold nanowire waveguides for plasmonic routers and logic gates.

机构信息

Beijing National Laboratory for Condensed Matter Physics, Institute of Physics, Chinese Academy of Sciences, Beijing 100190, China.

出版信息

Nanoscale. 2018 Jul 5;10(25):11923-11929. doi: 10.1039/c8nr01827h.

Abstract

Fabricating plasmonic nanowire waveguides and circuits by lithographic fabrication methods is highly desired for nanophotonic circuitry applications. Here we report an approach for fabricating metal nanowire networks by using electron beam lithography and metal film deposition techniques. The gold nanowire structures are fabricated on quartz substrates without using any adhesion layer but coated with a thin layer of Al2O3 film for immobilization. The thermal annealing during the Al2O3 deposition process decreases the surface plasmon loss. In a Y-shaped gold nanowire network, the surface plasmons can be routed to different branches by controlling the polarization of the excitation light, and the routing behavior is dependent on the length of the main nanowire. Simulated electric field distributions show that the zigzag distribution of the electric field in the nanowire network determines the surface plasmon routing. By using two laser beams to excite surface plasmons in a Y-shaped nanowire network, the output intensity can be modulated by the interference of surface plasmons, which can be used to design Boolean logic gates. We experimentally demonstrate that AND, OR, XOR and NOT gates can be realized in three-terminal nanowire networks, and NAND, NOR and XNOR gates can be realized in four-terminal nanowire networks. This work takes a step toward the fabrication of on-chip integrated plasmonic circuits.

摘要

通过光刻制造方法来制造等离子体纳米线波导和电路对于纳米光子学电路应用是非常需要的。在这里,我们报告了一种通过电子束光刻和金属薄膜沉积技术来制造金属纳米线网络的方法。金纳米线结构是在没有使用任何粘附层的情况下在石英衬底上制造的,但是涂有一层薄薄的 Al2O3 薄膜用于固定。在 Al2O3 沉积过程中的热退火会降低表面等离子体损耗。在 Y 型金纳米线网络中,可以通过控制激发光的偏振来将表面等离子体路由到不同的分支,并且路由行为取决于主纳米线的长度。模拟的电场分布表明,纳米线网络中电场的锯齿分布决定了表面等离子体的路由。通过使用两束激光来激发 Y 型纳米线网络中的表面等离子体,可以通过表面等离子体的干涉来调制输出强度,这可用于设计布尔逻辑门。我们通过实验证明,在三端纳米线网络中可以实现 AND、OR、XOR 和 NOT 门,在四端纳米线网络中可以实现 NAND、NOR 和 XNOR 门。这项工作朝着制造片上集成等离子体电路迈出了一步。

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