Siddiqui Mohammad Atif, Anwar M N, Laskar S H, Mahboob M R
Department of EIE, National Institute of Technology, Silchar 788010, India.
Department of Electrical Engineering, National Institute of Technology, Patna 800005, India.
ISA Trans. 2021 Aug;114:331-346. doi: 10.1016/j.isatra.2020.12.038. Epub 2020 Dec 22.
This article presents a unified approach of controller design in cascade control structure (CCS) for unstable, integrating and stable processes with dead-time to achieve enhanced load disturbance rejection. The design of inner and outer loop controllers in CCS is based, partially on the direct synthesis approach and partially on the pole placement method. First, the parameters of the inner loop controller are obtained and then the outer loop controller is designed by considering the inner loop as a part of the primary plant. The proposed design approach deals with a wide range of processes having unstable, integrating and stable dynamics in a unified way. It is applied directly on the higher and lower order processes, as the proposed strategy is acquitted from the approximation of the dead-time and model order reduction of the plant. Simulations have been conducted to show the efficacy of the present approach. The results shows that the present approach provides enhanced regulatory performance as compared to the recently reported approaches from the literature.
本文提出了一种在串级控制结构（CCS）中针对具有纯滞后的不稳定、积分和稳定过程进行控制器设计的统一方法，以实现增强的负载干扰抑制。CCS中内环和外环控制器的设计部分基于直接综合法，部分基于极点配置法。首先，获得内环控制器的参数，然后将内环视为主对象的一部分来设计外环控制器。所提出的设计方法以统一的方式处理具有不稳定、积分和稳定动态特性的广泛过程。它可直接应用于高阶和低阶过程，因为所提出的策略无需对纯滞后进行近似和降低对象的模型阶数。已进行仿真以展示本方法的有效性。结果表明，与文献中最近报道的方法相比，本方法提供了增强的调节性能。
