Wang Siyu, Shen Zhan, Sun Yali, Li Hui, Zhang Kaizhi, Wu Li, Ao Jianping, Zhang Yi
Institute of Photoelectronic Thin Film Devices and Technology and Tianjin Key Laboratory of Thin Film Devices and Technology, Nankai University, Tianjin 300350, China.
Institute of Electrical Engineering, Chinese Academy of Science, Beijing 100190, China.
ACS Appl Mater Interfaces. 2021 Mar 17;13(10):12211-12220. doi: 10.1021/acsami.1c00096. Epub 2021 Mar 7.
Heterojunction annealing is widely used to improve the efficiency of kesterite thin-film solar cells. However, the efficiency will decrease when the annealing temperature is high, and the reason why high-temperature postdeposition annealing results in the deterioration of device performance is not well-studied, which restricts the efficiency promotion of kesterite solar cells. This study investigates the effect of high-temperature postdeposition annealing on the p-n heterojunction and, thus, on the performance of the solar cell. The surface potential of the absorber layer inverts, the number of deep-level defects increases, and the CdS/CZTSe interface barrier height increases after high-temperature postdeposition annealing. A combination of different characterization methods reveals that excessive elemental diffusion at the p-n heterojunction during high-temperature postdeposition annealing is the key reason for deterioration of the performance of CZTSe devices. This study discloses the mechanism for the change in device properties with high-temperature postdeposition annealing and will also be helpful for understanding the mechanism of efficiency change as the solar cell keeps working.