Electronics Engineering Department, Faculty of Electronics and Electrical Engineering, University of Engineering and Technology, Taxila, Pakistan.
PLoS One. 2021 Mar 29;16(3):e0249269. doi: 10.1371/journal.pone.0249269. eCollection 2021.
Area efficient and high speed forward error correcting codes decoder are the demand of many high speed next generation communication standards. This paper explores a low complexity decoding algorithm of low density parity check codes, called the min-sum iterative construction a posteriori probability (MS-IC-APP), for this purpose. We performed the error performance analysis of MS-IC-APP for a (648,1296) regular QC-LDPC code and proposed an area and throughput optimized hardware implementation of MS-IC-APP. We proposed to use the layered scheduling of MS-IC-APP and performed other optimizations at architecture level to reduce the area and to increase the throughput of the decoder. Synthesis results show 6.95 times less area and 4 times high throughput as compared to the standard min-sum decoder. The area and throughput are also comparable to the improved variants of hard-decision bit-flipping (BF) decoders, whereas, the simulation results show a coding gain of 2.5 over the best implementation of BF decoder in terms of error performance.
面积高效和高速前向纠错码解码器是许多高速下一代通信标准的需求。本文探讨了一种用于低密度奇偶校验码的低复杂度解码算法，称为最小和迭代构造后验概率（MS-IC-APP），以满足这一需求。我们对 MS-IC-APP 进行了（648,1296）规则 QC-LDPC 码的误码性能分析，并提出了 MS-IC-APP 的面积和吞吐量优化的硬件实现。我们提出使用 MS-IC-APP 的分层调度，并在体系结构级别进行其他优化，以减少解码器的面积并提高吞吐量。综合结果表明，与标准最小和解码器相比，面积减少了 6.95 倍，吞吐量提高了 4 倍。与硬判决位翻转（BF）解码器的改进变体相比，面积和吞吐量也相当，而在误码性能方面，与 BF 解码器的最佳实现相比，模拟结果显示出 2.5 的编码增益。
