Pérez-López Daniel, Gutiérrez Ana, Capmany José
Opt Express. 2021 Mar 15;29(6):9043-9059. doi: 10.1364/OE.416053.
General-purpose programmable photonic processors rely on the large-scale integration of beamsplitters and reconfigurable phase shifters, distributed within unit cells or photonic gates. With their future evolution threatened by several hardware constrains, including the integration density that can be achieved with current mesh topologies, in this work, we present a unit cell topology design to increase the integration density of waveguide mesh arrangements based on folded Mach-Zehnder Interferometers. We report the design details of a 40-unit cell waveguide mesh integrated in a 11mm x 5.5 mm silicon nitride chip achieving, to the best of our knowledge, the highest integration density reported to date for a general-purpose photonic processor. The chip is electrically interfaced to a PCB and we report examples of reconfigurable optical beamsplitters, basic tunable microwave photonic filters with high peak rejection (40 dB approx.), as well as the dynamic interconnection and routing of 5G digitally modulated signals within the photonic mesh.
通用可编程光子处理器依赖于分束器和可重构移相器的大规模集成，这些元件分布在单元或光子门内。由于受到包括当前网格拓扑结构所能实现的集成密度在内的多种硬件限制，其未来发展受到威胁。在这项工作中，我们提出了一种单元拓扑设计，以提高基于折叠马赫-曾德尔干涉仪的波导网格排列的集成密度。我们报告了一个集成在11mm x 5.5mm氮化硅芯片中的40单元波导网格的设计细节，据我们所知，这是迄今为止报道的通用光子处理器中最高的集成密度。该芯片与印刷电路板进行电气连接，我们报告了可重构光分束器、具有高峰值抑制（约40dB）的基本可调谐微波光子滤波器的示例，以及5G数字调制信号在光子网格内的动态互连和路由。
