König Dirk, Frentzen Michael, Wilck Noël, Berghoff Birger, Píš Igor, Nappini Silvia, Bondino Federica, Müller Merlin, Gonzalez Sara, Di Santo Giovanni, Petaccia Luca, Mayer Joachim, Smith Sean, Knoch Joachim
Integrated Materials Design Laboratory (IMDL), The Australian National University, Canberra, Australian Capital Territory 2601, Australia.
Smart Materials and Surface Group, University of New South Wales, Sydney, New South Wales 2052, Australia.
ACS Appl Mater Interfaces. 2021 May 5;13(17):20479-20488. doi: 10.1021/acsami.0c22360. Epub 2021 Apr 20.
Impurity doping in silicon (Si) ultra-large-scale integration is one of the key challenges which prevent further device miniaturization. Using ultraviolet photoelectron spectroscopy and X-ray absorption spectroscopy in the total fluorescence yield mode, we show that the lowest unoccupied and highest occupied electronic states of ≤3 nm thick SiO-coated Si nanowells shift by up to 0.2 eV below the conduction band and ca. 0.7 eV below the valence band edge of bulk silicon, respectively. This nanoscale electronic structure shift induced by anions at surfaces (NESSIAS) provides the means for low-nanoscale intrinsic Si (i-Si) to be flooded by electrons from an external (bigger, metallic) reservoir, thereby getting highly electron- (n-) conductive. While our findings deviate from the behavior commonly believed to govern the properties of silicon nanowells, they are further confirmed by the fundamental energy gap as per nanowell thickness when compared against published experimental data. Supporting our findings further with hybrid density functional theory calculations, we show that other group IV semiconductors (diamond, Ge) do respond to the NESSIAS effect in accord with Si. We predict adequate nanowire cross-sections (X-sections) from experimental nanowell data with a recently established crystallographic analysis, paving the way to undoped ultrasmall silicon electronic devices with significantly reduced gate lengths, using complementary metal-oxide-semiconductor-compatible materials.
硅（Si）超大规模集成电路中的杂质掺杂是阻碍器件进一步小型化的关键挑战之一。我们使用紫外光电子能谱和全荧光产率模式下的X射线吸收光谱表明，厚度≤3 nm的SiO包覆的Si纳米阱的最低未占据电子态和最高占据电子态分别相对于体硅的导带向下移动高达0.2 eV，相对于价带边缘向下移动约0.7 eV。表面阴离子诱导的这种纳米级电子结构位移（NESSIAS）为低纳米级本征Si（i-Si）被来自外部（更大的金属）库的电子注入提供了途径，从而使其具有高电子（n-）导电性。虽然我们的发现偏离了通常认为决定硅纳米阱性质的行为，但与已发表的实验数据相比，根据纳米阱厚度的基本能隙进一步证实了这些发现。通过混合密度泛函理论计算进一步支持我们的发现，我们表明其他IV族半导体（金刚石、Ge）确实与Si一样对NESSIAS效应有响应。我们使用最近建立的晶体学分析从实验纳米阱数据预测出合适的纳米线横截面（X截面），为使用互补金属氧化物半导体兼容材料制造栅极长度显著减小的未掺杂超小硅电子器件铺平了道路。
