Yadav Manoj, Kashir Alireza, Oh Seungyeol, Nikam Revannath Dnyandeo, Kim Hyungwoo, Jang Hojung, Hwang Hyunsang
Centre for Single Atom-Based Semiconductor Device and Department of Materials Science and Engineering, Pohang University of Science and Technology (POSTECH), 77 Cheongam-ro, Nam-gu, Pohang 790784, Republic of Korea.
Institute of Physics ASCR, Na Slovance 2, 182 21 Prague 8, Czech Republic.
Nanotechnology. 2021 Dec 3;33(8). doi: 10.1088/1361-6528/ac3a38.
The formation of an interfacial layer is believed to affect the ferroelectric properties in HfObased ferroelectric devices. The atomic layer deposited devices continue suffering from a poor bottom interfacial condition, since the formation of bottom interface is severely affected by atomic layer deposition and annealing process. Herein, the formation of bottom interfacial layer was controlled through deposition of different bottom electrodes (BE) in device structure W/HZO/BE. The transmission electron microscopy (TEM) and x-ray photoelectron spectroscopy analyses done on devices W/HZO/W and W/HZO/IrOsuggest the strong effect of IrOin controlling bottom interfacial layer formation while W/HZO/W badly suffers from interfacial layer formation. W/HZO/IrOdevices show high remnant polarization (2) ∼ 53C cm, wake-up free endurance cycling characteristics, low leakage current with demonstration of low annealing temperature requirement as low as 350 °C, valuable for back-end-of-line integration. Further, sub-5 nm HZO thicknesses-based W/HZO/IrOdevices demonstrate high 2and wake-up free ferroelectric characteristics, which can be promising for low power and high-density memory applications. 2.2 nm, 3 nm, and 4 nm HZO based W/HZO/IrOdevices show 2values 13.54, 22.4, 38.23C cmat 4 MV cmand 19.96, 30.17, 48.34C cmat 5 MV cm, respectively, with demonstration of wake-up free ferroelectric characteristics.
据信,界面层的形成会影响基于HfO的铁电器件的铁电性能。原子层沉积器件的底部界面条件仍然很差,因为底部界面的形成受到原子层沉积和退火过程的严重影响。在此,通过在器件结构W/HZO/BE中沉积不同的底部电极(BE)来控制底部界面层的形成。对器件W/HZO/W和W/HZO/IrO进行的透射电子显微镜(TEM)和X射线光电子能谱分析表明,IrO在控制底部界面层形成方面具有很强的作用,而W/HZO/W在界面层形成方面存在严重问题。W/HZO/IrO器件显示出高剩余极化(2)约为53C/cm²,具有无唤醒疲劳循环特性,低漏电流,且证明所需的退火温度低至350°C,这对于后端集成很有价值。此外,基于厚度小于5nm的HZO的W/HZO/IrO器件表现出高剩余极化和无唤醒铁电特性,这对于低功耗和高密度存储器应用可能很有前景。基于2.2nm、3nm和4nm HZO的W/HZO/IrO器件在4MV/cm时的剩余极化值分别为13.54、22.4、38.23C/cm²,在5MV/cm时分别为19.96、30.17、48.34C/cm²,均表现出无唤醒铁电特性。