Wang Xiang, Zhang Zhun, Hao Qiang, Xu Dongdong, Wang Jiqing, Jia Haoyu, Zhou Zhiyu
School of Electronic and Information Engineering, Beihang University, Beijing 100191, China.
Micromachines (Basel). 2021 Nov 26;12(12):1450. doi: 10.3390/mi12121450.
The hardware security of embedded systems is raising more and more concerns in numerous safety-critical applications, such as in the automotive, aerospace, avionic, and railway systems. Embedded systems are gaining popularity in these safety-sensitive sectors with high performance, low power, and great reliability, which are ideal control platforms for executing instruction operation and data processing. However, modern embedded systems are still exposing many potential hardware vulnerabilities to malicious attacks, including software-level and hardware-level attacks; these can cause program execution failure and confidential data leakage. For this reason, this paper presents a novel embedded system by integrating a hardware-assisted security monitoring unit (SMU), for achieving a reinforced system-on-chip (SoC) on ensuring program execution and data processing security. This architecture design was implemented and evaluated on a Xilinx Virtex-5 FPGA development board. Based on the evaluation of the SMU hardware implementation in terms of performance overhead, security capability, and resource consumption, the experimental results indicate that the SMU does not lead to a significant speed degradation to processor while executing different benchmarks, and its average performance overhead reduces to 2.18% on typical 8-KB I/D-Caches. Security capability evaluation confirms the monitoring effectiveness of SMU against both instruction and data tampering attacks. Meanwhile, the SoC satisfies a good balance between high-security and resource overhead.
在众多安全关键型应用中，如汽车、航空航天、航空电子和铁路系统，嵌入式系统的硬件安全问题日益受到关注。嵌入式系统凭借高性能、低功耗和高可靠性，在这些对安全敏感的领域越来越受欢迎，是执行指令操作和数据处理的理想控制平台。然而，现代嵌入式系统仍然存在许多潜在的硬件漏洞，容易受到恶意攻击，包括软件级和硬件级攻击；这些攻击可能导致程序执行失败和机密数据泄露。因此，本文提出了一种新型嵌入式系统，通过集成硬件辅助安全监控单元（SMU），以实现强化的片上系统（SoC），确保程序执行和数据处理的安全。该架构设计在Xilinx Virtex-5 FPGA开发板上进行了实现和评估。基于对SMU硬件实现的性能开销、安全能力和资源消耗的评估，实验结果表明，在执行不同基准测试时，SMU不会导致处理器显著的速度下降，在典型的8KB I/D缓存上，其平均性能开销降至2.18%。安全能力评估证实了SMU对指令和数据篡改攻击的监控有效性。同时，该SoC在高安全性和资源开销之间实现了良好的平衡。
