Department of Information Engineering, University of Pisa, 56122 Pisa, Italy.
Sensors (Basel). 2021 Dec 24;22(1):121. doi: 10.3390/s22010121.
The design of advanced miniaturized ultra-low power interfaces for sensors is extremely important for energy-constrained monitoring applications, such as wearable, ingestible and implantable devices used in the health and medical field. Capacitive sensors, together with their correspondent digital-output readout interfaces, make no exception. Here, we analyse and design a capacitance-to-digital converter, based on the recently introduced iterative delay-chain discharge architecture, showing the circuit inner operating principles and the correspondent design trade-offs. A complete design case, implemented in a commercial 180 nm CMOS process, operating at 0.9 V supply for a 0-250 pF input capacitance range, is presented. The circuit, tested by means of detailed electrical simulations, shows ultra-low energy consumption (≤1.884 nJ/conversion), excellent linearity (linearity error 15.26 ppm), good robustness against process and temperature corners (conversion gain sensitivity to process corners variation of 114.0 ppm and maximum temperature sensitivity of 81.9 ppm/°C in the -40 °C, +125 °C interval) and medium-low resolution of 10.3 effective number of bits, while using only 0.0192 mm2 of silicon area and employing 2.93 ms for a single conversion.
对于能源受限的监测应用，如医疗领域中使用的可穿戴、可摄入和可植入设备，为传感器设计先进的小型超低功耗接口是非常重要的。电容式传感器及其对应的数字输出读取接口也不例外。在这里，我们分析并设计了一种基于最近提出的迭代延迟链放电架构的电容数字转换器，展示了电路的内部工作原理和相应的设计权衡。提出了一个完整的设计案例，该案例采用商用 180nm CMOS 工艺实现，在 0.9V 电源下工作，输入电容范围为 0-250pF。该电路通过详细的电气仿真进行了测试，具有超低的能耗（≤1.884nJ/转换）、优异的线性度（线性度误差 15.26ppm）、对工艺和温度角的良好鲁棒性（转换增益对工艺角变化的灵敏度为 114.0ppm，在-40°C至+125°C 温度范围内的最大温度灵敏度为 81.9ppm/°C）以及中等低分辨率的 10.3 有效位数，同时仅使用 0.0192mm2 的硅面积，单个转换耗时 2.93ms。
