Dang Hongmei, Ososanya Esther, Zhang Nian
Department of Electrical and Computer Engineering, University of the District of Columbia, United States of America.
Nanotechnology. 2022 Mar 4;33(21). doi: 10.1088/1361-6528/ac51eb.
CdS nanowires and film Schottky diodes are fabricated and diode properties are compared. Effect of SnOon CdS film diode properties is investigated. CdS film/Au on 100 nm SnOsubstrate demonstrates like-resistor characteristics and increase in SnOthickness corrects resistor behavior, however the effective reverse saturation current densityis significantly high and shunt resistance are considerably low, implying that SnOslightly prevents impurities migration from CdS films into ITO but cause additional issues. Thickness of CdS film on diode properties is further investigated and increasing CdS film thickness improvedby one order of magnitude, however shunt resistance is obviously low, suggesting intrinsic issues in CdS film. 100 nm CdS nanowire/Au diodes reduceby three orders of magnitude in the dark and two orders of magnitude in the light respectively and their shunt resistance is significantly enhanced by 70 times when comparing with those of the CdS film diodes. The wide difference can be attributed to the fact that CdS nanowires overcome intrinsic issues in CdS film and thus demonstrate significantly well- defined diode behavior. Simulation found that CdS nanowire diodes have low compensating acceptor type traps and interface state density of 5.0 × 10cm, indicating that interface recombination is not a dominated current transport mechanism in the nanowire diodes. CdS film diodes are simulated with acceptor traps and interface state density increased by two order of magnitude and shunt resistance reduced by one order of magnitude, indicating that high density of interface states and shunt paths occur in the CdS film diodes.
制备了硫化镉（CdS）纳米线和薄膜肖特基二极管，并对二极管特性进行了比较。研究了氧化锡（SnO）对CdS薄膜二极管特性的影响。在100纳米SnO衬底上的CdS薄膜/金表现出类似电阻的特性，增加SnO厚度可校正电阻行为，然而有效反向饱和电流密度显著较高，并联电阻相当低，这意味着SnO略微阻止了杂质从CdS薄膜迁移到氧化铟锡（ITO）中，但会引发其他问题。进一步研究了CdS薄膜厚度对二极管特性的影响，增加CdS薄膜厚度可使[此处原文似乎不完整，推测可能是某个参数]提高一个数量级，然而并联电阻明显较低，表明CdS薄膜存在固有问题。100纳米CdS纳米线/金二极管在黑暗中反向饱和电流密度降低三个数量级，在光照下降低两个数量级，与CdS薄膜二极管相比，其并联电阻显著提高了70倍。这种巨大差异可归因于CdS纳米线克服了CdS薄膜中的固有问题，从而表现出明显更明确的二极管行为。模拟发现，CdS纳米线二极管具有低补偿受主型陷阱，界面态密度为5.0×10[此处原文似乎不完整，推测可能是某个单位]，这表明界面复合不是纳米线二极管中主导的电流传输机制。对CdS薄膜二极管进行模拟时，受主陷阱和界面态密度增加两个数量级，并联电阻降低一个数量级，表示CdS薄膜二极管中存在高密度的界面态和并联路径。
