Ahmed Mohammed Altaf, Alnatheer Suleman
Department of Computer Engineering, College of Computer Engineering & Sciences, Prince Sattam Bin Abdulaziz University, Al-Kharj 11942, Saudi Arabia.
Micromachines (Basel). 2022 Jun 19;13(6):971. doi: 10.3390/mi13060971.
Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today's large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows-columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-In Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-In Self-Repair methods are developed on FPGA, and Verilog's simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches.
在存储器的容错方法中，包含冗余是一种常用且广泛应用的方式。有效的容错方法是当今大容量存储器的需求。近来，随着纳米技术的发展，片上系统（SOC）得以开发，其中大部分芯片面积被存储器占据。一般来说，SOC中的存储器包含各种大小且访问性较差。因此，使用传统的外部设备测试方法来修复这些存储器并不容易。出于这个原因，存储器设计者通常使用冗余方法，即用备用的行和列替换有故障的行和列，主要是为了提高存储器的良率。在本论文中，针对静态随机存取存储器（SRAM），提出了基于位交换线性反馈移位寄存器（BSLFSR）进行故障检测的深度Q学习（DQL）（DQL-BSLFSR-FD）。所提出的基于深度Q学习的存储器内建自测试（MBIST）用于检查存储器阵列单元是否存在故障。通过深度Q学习故障注入过程将故障插入到存储器中。在测试期间，使用不同的测试用例来控制测试模式和故障注入。随后，使用基于位交换线性反馈移位寄存器（BSLFSR）的内建自修复（BISR）模型，在存储器单元中插入故障后对故障存储器进行修复。BSLFSR模型执行冗余分析，利用备用的行和列而非有缺陷的单元来检测故障单元。所提出的BIST和内建自修复方法的设计与实现是在现场可编程门阵列（FPGA）上开发的，并进行了Verilog仿真。因此，所提出的DQL-BSLFSR-FD模型仿真的最大工作频率（最⼩时钟周期）比现有方法低23.5%、29.5%，总功耗比现有方法低34.9%、26.7%。
