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采用剪枝预均衡的44.2368 Gbit/s PAM8信号传输的现场可编程门阵列实现

FPGA implementation for 44.2368-Gbit/s PAM8 signal transmission with pruned pre-equalization.

作者信息

Wang Yikai, Chen Yu, Zhang Long, Xu Sicong, Wang Kaihui, Yu Jianjun

出版信息

Opt Lett. 2023 Sep 1;48(17):4562-4565. doi: 10.1364/OL.498579.

DOI:10.1364/OL.498579
PMID:37656555
Abstract

In this experiment, we demonstrated an intensity modulation and direct-detection (IM/DD) system based on a field-programmable gate array (FPGA). The PAM8 signals are successfully delivered at 44.2368 Gbit/s over a 45-km standard single-mode fiber (SSMF), satisfying the soft-decision forward error correction (SD-FEC) criterion of 2.4 × 10-, and the net bit rate may reach 36.864 Gbit/s without the need of optical amplifiers. At the transmitter, we used a pruned pre-equalization algorithm to process the PAM8 signals, and the high-speed parallel PAM8 signals were processed at the receiver using 64 parallel constant modulus algorithm (CMA) and decision-directed least mean square (DD-LMS) equalizers. Additionally, we analyzed the bit error rate (BER) performance of the DD-LMS equalizer in FPGA simulation with various data lengths, both before and after equalization.

摘要

在本实验中,我们展示了一种基于现场可编程门阵列(FPGA)的强度调制和直接检测(IM/DD)系统。PAM8信号在45公里标准单模光纤(SSMF)上以44.2368 Gbit/s的速率成功传输,满足2.4×10⁻⁴的软判决前向纠错(SD-FEC)标准,且无需光放大器时净比特率可达36.864 Gbit/s。在发射端,我们使用一种精简的预均衡算法来处理PAM8信号,在接收端使用64个并行恒模算法(CMA)和判决导向最小均方(DD-LMS)均衡器来处理高速并行PAM8信号。此外,我们在FPGA仿真中分析了不同数据长度下DD-LMS均衡器均衡前后的误码率(BER)性能。

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