Kim Ik-Jyae, Choi Jiwoung, Lee Jang-Sik
Department of Materials Science and Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Korea.
ACS Appl Mater Interfaces. 2024 Jul 3;16(26):33763-33770. doi: 10.1021/acsami.4c03785. Epub 2024 Jun 20.
Ferroelectric transistors are considered promising for next-generation 3D NAND technology due to their lower power consumption and faster operation compared to conventional charge-trap flash memories. However, ensuring their suitability for such applications requires a thorough investigation of array-scale reliability. This study specifically examines the suitability of hafnia-based ferroelectric transistors for advanced 3D NAND applications, with a specific focus on establishing a disturb-free voltage scheme to ensure the reliability of ferroelectric transistors within the array. Our key finding highlights the crucial role of optimal pass voltage in achieving disturb-free operation in both 2D and 3D ferroelectric NAND arrays. Additionally, the study indicates that read disturb remains negligible when an appropriate read voltage is applied. These insights provide a practical strategy for achieving reliable operation in 2D and 3D ferroelectric NAND, highlighting the potential of hafnia-based ferroelectric materials to meet the evolving requirements of high-density and reliable NAND flash memory applications.
与传统的电荷陷阱闪存相比，铁电晶体管因其较低的功耗和更快的运行速度而被认为在下一代3D NAND技术中具有潜力。然而，要确保它们适用于此类应用，需要对阵列规模的可靠性进行全面研究。本研究专门考察了基于氧化铪的铁电晶体管在先进3D NAND应用中的适用性，特别关注建立一种无干扰电压方案，以确保阵列中铁电晶体管的可靠性。我们的关键发现突出了最佳通过电压在二维和三维铁电NAND阵列中实现无干扰操作的关键作用。此外，该研究表明，当施加适当的读取电压时，读取干扰仍然可以忽略不计。这些见解为在二维和三维铁电NAND中实现可靠操作提供了一种实用策略，突出了基于氧化铪的铁电材料满足高密度和可靠NAND闪存应用不断发展的需求的潜力。
