Song Yunji, Park Sung-Min
Division of Electronic & Semiconductor Engineering, Ewha Womans University, Seoul 03760, Republic of Korea.
Graduate Program in Smart Factory, Ewha Womans University, Seoul 03760, Republic of Korea.
Micromachines (Basel). 2025 Feb 13;16(2):215. doi: 10.3390/mi16020215.
This paper introduces an analog differential optoelectronic receiver (ADOR) integrated with digital slicers for short-range LiDAR systems, consisting of a spatially modulated P/N-well on-chip avalanche photodiode (APD), a cross-coupled differential transimpedance amplifier (CCD-TIA) with cross-coupled active loads, a continuous-time linear equalizer (CTLE), a limiting amplifier (LA), and dual digital slicers. A key feature is the integration of an additional on-chip dummy APD at the differential input node, which enables the proposed ADOR to outperform a traditional single-ended TIA in terms of common-mode noise rejection ratio. Also, the CCD-TIA utilizes cross-coupled PMOS-NMOS active loads not only to generate the symmetric output waveforms with maximized voltage swings, but also to provide wide bandwidth characteristics. The following CTLE extends the receiver bandwidth further, allowing the dual digital slicers to operate efficiently even at high sampling rates. The LA boosts the output amplitudes to suitable levels for the following slicers. Then, the inverter-based slicers with low power consumption and a small chip area produce digital outputs. The fabricated ADOR chip using a 180 nm CMOS process demonstrates a 20 dB dynamic range from 100 μA to 1 mA, 2 Gb/s data rate with a 490 fF APD capacitance, and 22.7 mW power consumption from a 1.8 V supply.
本文介绍了一种用于短程激光雷达系统的集成数字限幅器的模拟差分光电接收器(ADOR),它由一个空间调制的P/N阱片上雪崩光电二极管(APD)、一个带有交叉耦合有源负载的交叉耦合差分跨阻放大器(CCD-TIA)、一个连续时间线性均衡器(CTLE)、一个限幅放大器(LA)和双数字限幅器组成。一个关键特性是在差分输入节点集成了一个额外的片上虚拟APD,这使得所提出的ADOR在共模噪声抑制比方面优于传统的单端TIA。此外,CCD-TIA利用交叉耦合的PMOS-NMOS有源负载,不仅可以生成具有最大电压摆幅的对称输出波形,还能提供宽带宽特性。接下来的CTLE进一步扩展了接收器带宽,使双数字限幅器即使在高采样率下也能高效运行。LA将输出幅度提升到适合后续限幅器的电平。然后,基于反相器的限幅器功耗低且芯片面积小,可产生数字输出。采用180 nm CMOS工艺制造的ADOR芯片在100 μA至1 mA范围内具有20 dB的动态范围,在APD电容为490 fF时数据速率为2 Gb/s,从1.8 V电源供电时功耗为22.7 mW。