Natani Shreyam, Khajanji Pranjali, Cheng Li, Eshraghi Kassra, Zhang Zichen, Shipley Wade, Tao Andrea R, Bandaru Prabhakar R
Department of Mechanical Engineering, University of California, San Diego, La Jolla, California 92093, United States.
Program in Materials Science, University of California, San Diego, La Jolla, California 92093, United States.
ACS Appl Mater Interfaces. 2025 Jun 4;17(22):32773-32781. doi: 10.1021/acsami.5c01721. Epub 2025 May 25.
It has been indicated that the path forward for the widespread usage of ferroelectric () materials may be considerably facilitated through the reduction of programming voltages to on-chip logic-compatible values of <1 V. Obstacles involve issues related to the scaling of the s to lower thickness as well as the presence of an interfacial layer (IL) between the high-permittivity and the substrate- resulting in voltage across the IL. Here, we show how lower operating voltages along with a higher tunneling electroresistance (TER) could be achieved through IL engineering. We use piezoresponse force microscopy and fabricated ferroelectric tunnel junctions (FTJs) to show that ultrathin FE films deposited on single-layer graphene/Si can exhibit polarization switching at reduced voltages ∼0.8 V with significant TER as compared to directly depositing on Si.
