FCRP Center on Functional Engineered Nano Architectonics, University of California, Los Angeles, CA 90095-1595, USA.
Adv Mater. 2010 Feb 9;22(6):769-78. doi: 10.1002/adma.200901689.
The semiconductor industry will soon be launching 32 nm complementary metal oxide semiconductor (CMOS) technology node using 193 nm lithography patterning technology to fabricate microprocessors with more than 2 billion transistors. To ensure the survival of Moore's law, alternative patterning techniques that offer advantages beyond conventional top-down patterning are aggressively being explored. It is evident that most alternative patterning techniques may not offer compelling advantages to succeed conventional top-down lithography for silicon integrated circuits, but alternative approaches may well indeed offer functional advantages in realising next-generation information processing nanoarchitectures such as those based on cellular, bioinsipired, magnetic dot logic, and crossbar schemes. This paper highlights and evaluates some patterning methods from the Center on Functional Engineered Nano Architectonics in Los Angeles and discusses key benchmarking criteria with respect to CMOS scaling.
半导体行业即将推出 32nm 互补金属氧化物半导体（CMOS）技术节点，采用 193nm 光刻技术来制造具有超过 20 亿个晶体管的微处理器。为了确保摩尔定律的持续发展，正在积极探索具有传统自上而下技术无法比拟优势的替代图案化技术。显然，大多数替代图案化技术可能无法为传统的硅集成电路自上而下光刻提供有吸引力的优势，但替代方法确实可能在实现基于细胞、生物启发、磁点逻辑和交叉线方案等下一代信息处理纳米架构方面提供功能优势。本文重点介绍和评估了洛杉矶功能工程纳米结构中心的一些图案化方法，并讨论了与 CMOS 缩放相关的关键基准测试标准。
