Radamson Henry H, Zhu Huilong, Wu Zhenhua, He Xiaobin, Lin Hongxiao, Liu Jinbiao, Xiang Jinjuan, Kong Zhenzhen, Xiong Wenjuan, Li Junjie, Cui Hushan, Gao Jianfeng, Yang Hong, Du Yong, Xu Buqing, Li Ben, Zhao Xuewei, Yu Jiahan, Dong Yan, Wang Guilei
Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China.
Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China.
Nanomaterials (Basel). 2020 Aug 7;10(8):1555. doi: 10.3390/nano10081555.
The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.
国际半导体技术路线图（ITRS）正接近历史终点，我们观察到半导体行业正将互补金属氧化物半导体（CMOS）进一步推向未知领域。由于按照摩尔定律缩小了栅极和源极/漏极区域，如今具有三维结构并集成了先进应变工程的晶体管与最初的平面二维晶体管有了根本区别。本文综述了在ITRS技术接近尾声之际，纳米级晶体管的新架构、模拟方法和工艺技术。讨论内容涵盖了器件加工中的创新方法、挑战和困难，以及可能在不久的将来出现的新计量技术。
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