Kim Jungsuk, Pedrotti Kenneth
Department of Electrical Engineering, University of California at Santa Cruz, CA 95064, USA.
Annu Int Conf IEEE Eng Med Biol Soc. 2010;2010:1573-6. doi: 10.1109/IEMBS.2010.5626686.
This paper presents a low-power and self-biased neural amplifier for implantable EEG recording system ICs with a high-density interface. To achieve low-power consumption, small die-area, high gain, and high CMRR, a fully differential Chappell OTA is employed along with a capacitive feedback loop. The amplifier operating at ± 1.2V has a gain of 65.6dB and consumes a power of 1.7 microW. The bandwidth extends from a low-frequency cutoff of below 1 Hz to a high-frequency cutoff of 300Hz which is suitable for EEG signals. This proposed amplifier has an input-referred noise of 9.76 mmicroV(RMS) and THD of 1.86% with respect to 1mV(PP) input at 100Hz. This low-power self-biased neural amplifier occupies an active die-area of 0.244 mm(2) and is under fabrication in 0.35 microm CMOS 4M2P Process.
本文提出了一种用于具有高密度接口的植入式脑电图记录系统集成电路的低功耗自偏置神经放大器。为了实现低功耗、小芯片面积、高增益和高共模抑制比，采用了全差分查佩尔运算跨导放大器以及电容反馈回路。该放大器在±1.2V电压下工作，增益为65.6dB，功耗为1.7微瓦。带宽从低于1Hz的低频截止扩展到300Hz的高频截止，适用于脑电图信号。该拟议放大器在100Hz时，相对于1mV（峰峰值）输入，输入参考噪声为9.76微伏（均方根值），总谐波失真为1.86%。这种低功耗自偏置神经放大器的有源芯片面积为0.244平方毫米，正在采用0.35微米互补金属氧化物半导体4M2P工艺进行制造。
Zotero 插件