Ruiz-Amaya Jesus, Rodriguez-Perez Alberto, Delgado-Restituto Manuel
Institute of Microelectronics of Seville, Avda. Americo Vespucio s/n, Sevilla 41092, Spain.
Sensors (Basel). 2015 Sep 30;15(10):25313-35. doi: 10.3390/s151025313.
This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency factor under area and noise constraints. The proposed LNA has been implemented in a 130 nm CMOS technology and occupies 0.053 mm-sq. Experimental results show that the LNA offers a noise efficiency factor of 2.16 and an input referred noise of 3.8 μVrms for 1.2 V power supply. It provides a gain of 46 dB over a nominal bandwidth of 192 Hz-7.4 kHz and consumes 1.92 μW. The performance of the proposed LNA has been validated through in vivo experiments with animal models.
本文介绍了一种用于神经尖峰记录应用的低噪声放大器（LNA）。所提出的拓扑结构基于使用两级运算跨导放大器（OTA）的电容反馈网络，有效解决了功率、面积和噪声之间的三重权衡问题。此外，这项工作引入了一种新颖的晶体管级合成方法，用于在面积和噪声约束下将LNA的噪声效率因子最小化。所提出的LNA已采用130nm CMOS技术实现，占用面积为0.053平方毫米。实验结果表明，对于1.2V电源，该LNA的噪声效率因子为2.16，输入参考噪声为3.8μVrms。它在192Hz - 7.4kHz的标称带宽上提供46dB的增益，功耗为1.92μW。所提出的LNA的性能已通过动物模型的体内实验得到验证。
