Zhang Yanbo, Xiong Ying, Yang Xiang, Wang Ying, Han Weihua, Yang Fuhua
Research Center of Semiconductor Integration Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China.
J Nanosci Nanotechnol. 2010 Nov;10(11):7113-6. doi: 10.1166/jnn.2010.2811.
SOI based wrap-gate silicon nanowire FETs are fabricated through electron beam lithography and wet etching. Dry thermal oxidation is used to further reduce the patterned fins cross section and transfer them into nanowires. Silicon nanowire FETs with different nanowire widths varying from 60 nm to 200 nm are fabricated and the number of the nanowires contained in a channel is also varied. The on-current (I(ON)) and off-current (I(OFF)) of the fabricated silicon nanowire FET are 0.59 microA and 0.19 nA respectively. The subthreshold swing (SS) and the drain induced barrier lowering are 580 mV/dec and 149 mV/V respectively due to the 30 nm thick gate oxide and 10(15) cm(-3) lightly doped silicon nanowire channel. The nanowire width dependence of SS is shown and attributed to the fact that the side-gate parts of a wrap gate play a more effectual role as the nanowires in a channel get narrower. It seems the nanowire number in a channel has no effect on SS because the side-gate parts fill in the space between two adjacent nanowires.
基于绝缘体上硅（SOI）的环绕栅硅纳米线场效应晶体管通过电子束光刻和湿法蚀刻制造。干式热氧化用于进一步减小图案化鳍片的横截面并将其转变为纳米线。制造出了具有不同纳米线宽度（从60纳米到200纳米）的硅纳米线场效应晶体管，并且沟道中包含的纳米线数量也有所变化。所制造的硅纳米线场效应晶体管的导通电流（I(ON)）和截止电流（I(OFF)）分别为0.59微安和0.19纳安。由于30纳米厚的栅极氧化物和10(15)厘米(-3)的轻掺杂硅纳米线沟道，亚阈值摆幅（SS）和漏极感应势垒降低分别为580毫伏/十倍对数和149毫伏/伏。展示了SS对纳米线宽度的依赖性，并归因于这样一个事实：随着沟道中的纳米线变窄，环绕栅的侧栅部分发挥着更有效的作用。似乎沟道中的纳米线数量对SS没有影响，因为侧栅部分填充了相邻两根纳米线之间的空间。
