IBM T.J. Watson Research Center, Yorktown Heights, New York 10598, USA.
ACS Nano. 2011 Jul 26;5(7):5848-54. doi: 10.1021/nn201611r. Epub 2011 Jun 21.
Electrostatically doped graphene p-n junctions can be formed by applying large source-drain and source-gate biases to a graphene field-effect transistor, which results in trapped charges in part of the channel gate oxide. We measure the temperature distribution in situ during the electrical stress and characterize the resulting p-n junctions by Raman spectroscopy and photocurrent microscopy. Doping levels, the size of the doped graphene segments, and the abruptness of the p-n junctions are all extracted. Additional voltage probes can limit the length of the doped segments by acting as heat sinks. The spatial location of the identified potential steps coincides with the position where a photocurrent is generated, confirming the creation of p-n junctions.
通过向石墨烯场效应晶体管施加大的源漏和源栅偏压，可以形成静电掺杂的石墨烯 p-n 结，这会导致部分沟道栅氧化层中的俘获电荷。我们在电应力过程中进行原位测量温度分布，并通过拉曼光谱和光电流显微镜来表征所得到的 p-n 结。提取掺杂水平、掺杂石墨烯段的大小以及 p-n 结的陡度。附加的电压探头可以通过充当散热器来限制掺杂段的长度。确定的电势阶跃的空间位置与产生光电流的位置重合，从而证实了 p-n 结的形成。
