Mountney John, Obeid Iyad, Silage Dennis
Electrical & Computer Engineering, Temple University, Philadelphia, PA, USA.
Annu Int Conf IEEE Eng Med Biol Soc. 2011;2011:4617-20. doi: 10.1109/IEMBS.2011.6091143.
As the computational complexities of neural decoding algorithms for brain machine interfaces (BMI) increase, their implementation through sequential processors becomes prohibitive for real-time applications. This work presents the field programmable gate array (FPGA) as an alternative to sequential processors for BMIs. The reprogrammable hardware architecture of the FPGA provides a near optimal platform for performing parallel computations in real-time. The scalability and reconfigurability of the FPGA accommodates diverse sets of neural ensembles and a variety of decoding algorithms. Throughput is significantly increased by decomposing computations into independent parallel hardware modules on the FPGA. This increase in throughput is demonstrated through a parallel hardware implementation of the auxiliary particle filtering signal processing algorithm.
随着脑机接口（BMI）神经解码算法的计算复杂度增加，通过顺序处理器来实现这些算法对于实时应用来说变得难以承受。这项工作提出将现场可编程门阵列（FPGA）作为用于BMI的顺序处理器的替代方案。FPGA的可重新编程硬件架构为实时执行并行计算提供了近乎最优的平台。FPGA的可扩展性和可重新配置性能够适应不同的神经集合组以及各种解码算法。通过将计算分解为FPGA上独立的并行硬件模块，吞吐量得到显著提高。通过辅助粒子滤波信号处理算法的并行硬件实现展示了这种吞吐量的提升。
