Mountney John, Silage Dennis, Obeid Iyad
Department of Electrical and Computer Engineering, Temple University, Philadelphia, PA 19122, USA.
Annu Int Conf IEEE Eng Med Biol Soc. 2010;2010:2674-7. doi: 10.1109/IEMBS.2010.5626626.
Both linear and nonlinear estimation algorithms have been successfully applied as neural decoding techniques in brain machine interfaces. Nonlinear approaches such as Bayesian auxiliary particle filters offer improved estimates over other methodologies seemingly at the expense of computational complexity. Real-time implementation of particle filtering algorithms for neural signal processing may become prohibitive when the number of neurons in the observed ensemble becomes large. By implementing a parallel hardware architecture, filter performance can be improved in terms of throughput over conventional sequential processing. Such an architecture is presented here and its FPGA resource utilization is reported.
线性和非线性估计算法都已成功应用于脑机接口中的神经解码技术。诸如贝叶斯辅助粒子滤波器之类的非线性方法相较于其他方法能提供更好的估计，但其代价似乎是计算复杂度较高。当观测总体中的神经元数量变得很大时，用于神经信号处理的粒子滤波算法的实时实现可能会变得难以实现。通过实现并行硬件架构，可以在吞吐量方面相较于传统顺序处理提高滤波器性能。本文介绍了这样一种架构，并报告了其FPGA资源利用率。
