School of Electronic and Electrical Engineering, University of Leeds, Leeds, UK.
IEEE Trans Ultrason Ferroelectr Freq Control. 2012 Jan;59(1):40-9. doi: 10.1109/TUFFC.2012.2154.
Coarse time quantization of delay profiles within ultrasound array systems can produce undesirable side lobes in the radiated beam profile. The severity of these side lobes is dependent upon the magnitude of phase quantization error--the deviation from ideal delay profiles to the achievable quantized case. This paper describes a method to improve interchannel delay accuracy without increasing system clock frequency by utilizing embedded phase-locked loop (PLL) components within commercial field-programmable gate arrays (FPGAs). Precise delays are achieved by shifting the relative phases of embedded PLL output clocks in 208-ps steps. The described architecture can achieve the necessary interelement timing resolution required for driving ultrasound arrays up to 50 MHz. The applicability of the proposed method at higher frequencies is demonstrated by extrapolating experimental results obtained using a 5-MHz array transducer. Results indicate an increase in transmit dynamic range (TDR) when using accurate delay profiles generated by the embedded-PLL method described, as opposed to using delay profiles quantized to the system clock.
超声阵列系统中延迟轮廓的粗时量化会在辐射波束轮廓中产生不希望的旁瓣。这些旁瓣的严重程度取决于相位量化误差的大小——即从理想延迟轮廓到可实现的量化情况的偏差。本文介绍了一种通过利用商用现场可编程门阵列 (FPGA) 中的嵌入式锁相环 (PLL) 组件来提高通道间延迟精度而不增加系统时钟频率的方法。通过以 208-ps 的步长移动嵌入式 PLL 输出时钟的相对相位来实现精确的延迟。所描述的架构可以实现驱动高达 50 MHz 的超声阵列所需的必要元件间定时分辨率。通过外推使用 5 MHz 阵列换能器获得的实验结果，证明了该方法在更高频率下的适用性。结果表明，与使用量化到系统时钟的延迟轮廓相比，使用嵌入式 PLL 方法生成的精确延迟轮廓可以提高发射动态范围 (TDR)。
