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用于实现集成电路和器件进步的光刻技术。

Lithography for enabling advances in integrated circuits and devices.

机构信息

Garner Nanotechnology Solutions, Stanford University, Stanford, CA, USA.

出版信息

Philos Trans A Math Phys Eng Sci. 2012 Aug 28;370(1973):4015-41. doi: 10.1098/rsta.2011.0052.

Abstract

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

摘要

由于晶体管是大规模制造的,光刻技术使得器件和集成电路的密度得以提高。随着集成电路的发明,光刻技术通过光学光刻的不断发展应用,使得场效应晶体管的集成密度更高。1994 年,半导体行业确定继续提高晶体管的密度越来越困难,需要光刻和工艺能力的协调发展。它制定了美国半导体国家技术路线图,该路线图于 1999 年扩展为国际半导体技术路线图,以协调多个行业提供复杂的能力,继续将集成电路的密度提高到纳米尺度。自 20 世纪 60 年代以来,随着从接触式打印机到步进光刻机的发展,光刻技术变得越来越复杂,采用 i 线、248nm 和 193nm 波长的图形缩减技术,这需要大幅提高掩模制造技术、光刻印刷和对准能力以及光刻胶能力。同时,图形转移已经从特征的湿法刻蚀发展到等离子体刻蚀和更复杂的刻蚀能力,以制造目前在大批量生产中 32nm 的特征。为了继续提高器件和互连的密度,需要新的图形转移技术,未来可能包括极紫外光刻、压印技术和定向自组装。虽然互补金属氧化物半导体在未来许多年内仍将得到扩展,但这些先进的图形转移技术可能会为未来基于不同物理现象的新型存储和逻辑技术的发展提供支持,从而增强和扩展信息处理能力。

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