Suppr超能文献

用于集成纳米电子器件的碳纳米管晶圆的分层三维层层组装。

Hierarchical three-dimensional layer-by-layer assembly of carbon nanotube wafers for integrated nanoelectronic devices.

机构信息

Nanotube Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba 305-8565, Japan.

出版信息

Nano Lett. 2012 Sep 12;12(9):4540-5. doi: 10.1021/nl3016472. Epub 2012 Aug 17.

Abstract

We report a general approach to overcome the enormous obstacle of the integration of CNTs into devices by bonding single-walled carbon nanotubes (SWNTs) films to arbitrary substrates and transferring them into densified and lithographically processable "CNT wafers". Our approach allows hierarchical layer-by-layer assembly of SWNTs into organized three-dimensional structures, for example, bidirectional islands, crossbar arrays with and without contacts on Si, and flexible substrates. These organized SWNT structures can be integrated with low-power resistive random-access memory.

摘要

我们报告了一种通用方法,通过将单壁碳纳米管 (SWNTs) 薄膜键合到任意基底上并将其转化为致密且可光刻处理的“CNT 晶圆”,来克服将 CNT 集成到器件中的巨大障碍。我们的方法允许 SWNTs 进行分层逐层组装,形成有组织的三维结构,例如,双向岛、有和没有 Si 接触的叉指数组,以及柔性基底。这些有组织的 SWNT 结构可以与低功耗电阻式随机存取存储器集成。

文献AI研究员

20分钟写一篇综述,助力文献阅读效率提升50倍。

立即体验

用中文搜PubMed

大模型驱动的PubMed中文搜索引擎

马上搜索

文档翻译

学术文献翻译模型,支持多种主流文档格式。

立即体验