Department of Chemical and Biomolecular Engineering, National University of Singapore, Blk E5, 4 Engineering Drive 4, Singapore 117576.
ACS Appl Mater Interfaces. 2013 Jun 26;5(12):5727-32. doi: 10.1021/am401189p. Epub 2013 Jun 4.
Fabrication of high density (~155 Gbit in(-2)) ZnO nanopatterns through in situ decomposition of Zn precursors inside diblock copolymer templates and their application as charge storage centers in nonvolatile memory devices is described. The fabrication is performed in a highly controlled fashion with the resulting ZnO nanopatterned arrays exhibiting diameters of 38 nm and heights of 14 nm offering sub-50 nm feature resolutions. The ZnO nanopatterns are naturally n-type due to the presence of zinc interstitials and oxygen vacancies that act as defect levels in trapping charge carriers. Test capacitors (metal-oxide-semiconductor, MOS) constructed using nanopatterns formed on p-Si exhibited a large flatband voltage shift of about ~2.2 V for a low operating voltage of 10 V. A high charge trap density of 3.47 × 10(18) cm(-3) combined with a good retention capacity is observed with low tunneling oxide (thermally grown) thickness of 3 nm. This demonstrates the significant promise of the ZnO nanopatterned arrays to act as charge storage centers for potential application in nonvolatile flash memory devices. The charge trapping characteristics, the capacitance-voltage measurements, and the potential of ZnO nanopatterns as charge storage centers in fabricating nonvolatile memory devices are discussed.
通过在两亲嵌段共聚物模板内原位分解锌前体来制造高密度(~155 Gbit/in^2)的 ZnO 纳米图案,并将其用作非易失性存储器件中的电荷存储中心,本文对此进行了描述。该制造过程采用高度受控的方式进行,所得 ZnO 纳米图案化阵列的直径为 38nm,高度为 14nm,提供了小于 50nm 的特征分辨率。由于锌间隙和氧空位的存在,ZnO 纳米图案呈现出自然的 n 型,这些缺陷能级可以捕获电荷载流子。使用在 p-Si 上形成的纳米图案制造的测试电容器(金属-氧化物-半导体,MOS),在低工作电压为 10V 的情况下,表现出约 2.2V 的大平带电压偏移。观察到具有 3nm 低热生长氧化层厚度的 3.47×10^18cm^-3 高电荷俘获密度和良好的保持能力,这表明 ZnO 纳米图案阵列作为电荷存储中心具有很大的应用潜力,可用于非易失性闪存器件。本文讨论了电荷俘获特性、电容-电压测量以及 ZnO 纳米图案作为电荷存储中心在制造非易失性存储器件中的潜力。